In telecommunication systems, node equipment transmits and receives data from each other through a transmission network connecting the nodes. Data cannot be received correctly unless the clock of the receiving circuit is synchronised with the frequency and phase of the incoming data. Almost without exception, the clock frequency of the receiving circuit is formed by a PLL (Phase Locked Loop).
The purpose of the phase lock is to remove jitter, migration and other interfering components occurring in the synchronisation signal. A long transmission distance will affect signal quality, and a distorted input signal makes great demands on the clock signal regeneration block.
If a trouble situation occurs on the route of the synchronisation signal, another synchronisation source may have to be used, whereby the phase lock will exchange the synchronisation source, which worked as reference, for another synchronisation source. Also during a change of the network structure and during network element updates such a situation may occur, when the phase lock of the receiving equipment must change the synchronisation source. The phase lock must be able to cope also with such situations.
A typical phase lock structure is shown in FIG. 1. The phase difference meter 13 compares the phase difference between signal P1 selected as reference signal and signal P2 formed by dividing from oscillator signal P3 by calculating, how many pulses of oscillator signal P3 can be accommodated between the rising or falling edges of the signals to be compared. For example, the frequency of signal P2 may be two times the frequency of signal P1. The frequency of signal P3 is considerably higher than the frequencies of signals P1 and P2.
Microcomputer 14 must form a control word for the D/A converter. The control word is obtained from the results of measurements performed by phase difference meter 13. From measurements obtained during a certain measuring period, the microcomputer calculates an average, which together with an average calculated earlier is used for forming the control word.
D/A converter 15 converts the control word from digital form into analog form, which after the conversion is supplied to crystal oscillator 16. The crystal oscillator generates signal P3, which is used for generating signal P2 for use in the phase difference measurement.
Divider 18 receives signal P3 from cut-off circuit 17 of the oscillator signal. The cut-off circuit is intended to control the exchange of synchronisation signal sources. If for some reason it is desired in selection circuit 12 to exchange the signal of synchronisation source 10 for the signal of another synchronisation source 11, then the microcomputer 14 of the phase lock will with signal CUTC prevent the oscillator signal from having access to the divider forming signal P2 for a time T at a time. After the cut-off, the phase of signal P2 seen by the phase difference meter will transfer by time constant T compared with the phase of signal P1. By performing a suitable number of signal cut-off operations and by reading the value of the phase difference meter after each cut-off, it is possible to set the phase difference of signals P1 and P2, whose phases are compared, with an accuracy of time constant T at the average SETM of the phase meter. Thus, the phase difference is transferred by successive cut-offs as close as possible to the above-mentioned average.
FIG. 1 shows the structure of a typical state-of-the-art phase lock. It is obvious that the structure can also be of another kind. For example, divider 18 and the signal cut-off function 17 may be functionally connected between selection circuit 12 of the synchronisation input and phase difference meter 13. Hereby the microcomputer will give a cut-off command CUTC to cut off signal P1. There may be a divider and a cut-off circuit also in both the places mentioned.
In FIG. 2 a dashed line illustrates a situation, where a cut-off operation taking place during a change of synchronisation signal has allocated the phase of signal P2 at a desired value with a precision of time constant T. The selected setting value is an average SETM of the maximum possible number of pulses between the above-mentioned rising or falling edges. Signal P2 shown by a solid line shows the desired relative location of phases.
FIG. 3 shows a time slot of the calculation to be performed in the phase difference meter. In this example, the calculation starts from the rising edge of signal P1 and ends at the following rising edge of signal P2.
The phase lock is started after the phase setting described above, whereby the phase difference will set at setting value SETM within a certain setting time. During the setting time, such an undesirable phase transfer occurs in the output signal of the phase lock, which may cause transfer errors or e.g. buffer overflows.
FIG. 4 illustrates in flow chart form a state-of-the-art method for changing the synchronisation source in a phase lock. When a decision on exchange of synchronisation signal is desired in the system (step 48), a change measure is taken (step 41). If a change of synchronisation signal is not desired, the phase lock continues to maintain the phase difference at its setting value SETM (step 47).
After the change of synchronisation signal, the phase difference meter measures the phase difference SETC (step 42). The measurement value of the phase difference meter is compared with the phase difference setting value (step 43). If the absolute value of their difference is higher than the value of time constant T, an oscillator signal cut-off operation is performed (step 44) by giving a CUTC command. But if the said absolute value is lower than or equal to the value of time constant T, then the adjustment algorithm of the phase lock is started in step 45. The adjustment algorithm aims at adjusting the phase difference at its setting value SETM (step 46). When the setting value is reached, the adjustment algorithm will aim at maintaining the phase difference at its setting value (step 47).
The phase transfer occurring in the change of synchronisation source is a problem with the state of the art described in the foregoing. This phase error is seen in the output signal, and it may cause trouble situations, such as e.g. transfer errors or buffer overflows.
The present invention aims at avoiding the described state-of-the-art problem. This aim is achieved in the manner described in the independent claims.